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Very long instruction work architectures and the ELI-512

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1 Author(s)
Joseph A. Fisher ; Yale University

By compiling ordinary scientific applications programs with a radical technique called trace scheduling, we are generating code for a parallel machine that will run these programs faster than an equivalent sequential machine - we expect 10 to 30 times faster. Trace scheduling generates code for machines called very long instruction work architectures. In very long instruction word machines, many statically scheduled, tightly coupled, fine-grained operations exwcute in parallel with a single instruction stream. VLIWs are more parallel extensions of several current architectures. These current architectures have never cracked a fundamental barrier. The speedup they get from parallelism is never more than a factor of 2 to 3. Not htat we couldn't build more parallel machines of this type: but until trace scheduling we did't know how to generate code for them. Trace scheduling finds sufficient paralleslism in ordinary code to justify thinking about a highly parallel VLIW. At Yale we are actualy buildingone. Our machine, the ELI-512 has a horizontal instruction word of over 500 bits and will do 10 to 30 RISC-level operations per cyple [Patterson 82]. ELI stands for Enormously Longword Instructions; 512 is the size of the instruction word we hope to achieve. (The current design has a 1200-bit instruction word).

Published in:

IEEE Solid-State Circuits Magazine  (Volume:1 ,  Issue: 2 )