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Control and synchronization scheme for parallel image processing RAM with 128 processor elements and 16-Mb DRAM

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11 Author(s)
Y. Yabe ; NEC Corp., Kanagawa, Japan ; T. Kimura ; Y. Aimoto ; H. Heiuchi
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A newly developed parallel image processing RAM (PIP-RAM) integrates 128 processor elements and a 16-Mb DRAM on a single chip. The paper presents three novel circuit design techniques: a data path control and synchronization scheme between processors and memory; a refresh scheme which enables refresh operations in parallel with arithmetic-logical operations; and a special block redundancy scheme

Published in:

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Date of Conference:

5-8 May 1996