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Exploring the power dimension [in digital CMOS]

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1 Author(s)
Rabaey, J.M. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Keeping the power dissipation within bounds is rapidly becoming one of the main challenges in contemporary digital design. Design experience and research in the early 1990s has amply demonstrated that doing so requires a “power conscious” design methodology that addresses dissipation at every level of the design hierarchy. Evidently, this cannot be achieved if no accompanying design automation environment is available. Spurred by this observation, we have seen an intensive effort in the domain of design automation for low power in recent years that has resulted in both academic and industrial tool environments. In this tutorial, we only focus on the analysis facet of the low power design process. Not only is the availability of analysis, simulation, and prediction tools the “conditio sine qua non” for low power design, it also represents the most understood and established component of the low-power design methodology. The paper starts with a discussion of power analysis at the circuit and logic design abstraction levels. This domain is becoming relatively mature with multiple entries commercially available. In our opinion, it is the high-level power prediction however that will have the most impact on the reduction of power dissipation. We have therefore included an in-depth discussion on the efforts and results in the so-called “power exploration” domain, that includes power prediction and analysis at the RTL level and above

Published in:

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Date of Conference:

5-8 May 1996