By Topic

Analog routing for manufacturability

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Lampaert, K. ; ESAT, Katholieke Univ., Leuven, Heverlee, Belgium ; Gielen, G. ; Sansen, W.

The goal of a performance-driven routing tool is to route an analog circuit such that the performance degradation caused by layout parasitics remains within the specification margins imposed by the designer. For a given set of circuit specifications, several valid routing solutions can be found. In this paper, we propose an algorithm that selects the solution that additionally maximizes the yield and the testability of the resulting layout. Initially, the circuit is routed with a cost function designed to enforce all performance constraints. After all nets have been routed, the layout parasitics are extracted and the performance of the circuit is verified. In a second phase, nets are ripped up and rerouted to optimize the yield and the testability of the layout. During this process, care is taken not to introduce performance constraint violations. An industrial example, is presented to demonstrate the effectiveness of the approach

Published in:

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Date of Conference:

5-8 May 1996