By Topic

Power management technique for 1-V LSIs using embedded processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
S. Shigematsu ; NTT LSI Labs., Atsugi, Japan ; S. Mutoh ; Y. Matsuya

A new power management technique is proposed for low-power, high-speed LSIs. This technique reduces the power consumption and enhances the performance of an LSI by using an embedded small processor to control the sleep modes and the processing of the LSI. Using this technique for a low-power DSP, the total power is reduced to about 10% of one without this technique, while maintaining the speed performance in 1-V LSIs

Published in:

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Date of Conference:

5-8 May 1996