By Topic

A pipelined digital differential matched filter FPGA implementation and VLSI design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kuang-Chan Liu ; Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan ; Wun-Chang Lin ; Chorng-Kuang Wang

A digital matched filter having a differential and pipelined structure is proposed for CDMA (Code Division Multiple Access) communication systems. A novel differential PN (Pseudo-Noise) code scheme is adopted to reduce the number of multiplication and summation (M&S). The PDDMF (Pipelined Digital Differential Matched Filter) not only saves half of the hardware and power, but also improves the speed to a single operation time of M&S. These features make the PDDMF more suitable for personal communication high speed and low power requirements than the conventional methods. The FPGA of the DDMF (Digital Differential Matched Filter) verifies the matched filter using the proposed differential PN code scheme. Moreover, a 64 taps length PDDMF with 4 bits soft decision using 5 V 0.8 μm CMOS standard cells is designed. The active chip area is 2.6×2.6 mm2. Simulation results demonstrate that the chip rate of the PN code in the PDDMF can achieve 45 M chips/sec

Published in:

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Date of Conference:

5-8 May 1996