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A high speed CMOS signalling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes 1-V push-pull drivers, a Delay Line PLL and sampling of the data on both half-periods of the clock. In order to increase the noise immunity of the reception, current-integrating receivers are used to sample the data in the input pads. Chips fabricated in 0.8-/spl mu/m CMOS technology achieve transfer rates of 740 Mbits/sec/pin operating from a 3.3-V supply with a bit error rate of less than 10/sup -14/.