Cart (Loading....) | Create Account
Close category search window
 

A 285 MHz 6-port plesiochronous router chip with non-blocking cross-bar switch

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

13 Author(s)
Mu, A. ; HAL Comput. Syst., Cambell, CA, USA ; Chia, B. ; Kondapalli, S. ; Koo, C.
more authors

The HAL router chip is a 285 MHz 6-port plesiochronous packet-switched routing chip with non-blocking cross-bar switch. It combines very high bandwidth (4.5 GByte/s per port, 27 GByte/s total raw bandwidth), low fall-through latency (32 ns), no internal blocking, three arbitration priorities with in-order delivery, a flexible source routing scheme, virtual-cut-through routing, and robust reverse flow control.

Published in:

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Date of Conference:

13-15 June 1996

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.