Referenced Items are not available for this document.
This paper describes an I/O scheme for use as a high-speed bus which eliminates setup and hold time requirements between clock and data by using oversampling method. The I/O circuit uses low jitter PLL which suppresses the effect of supply noise. Two experimental chips with 4 pin interface have been fabricated with 0.6 /spl mu/m CMOS technology, which exhibits the bandwidth of 960 Mbps per pin.
Published in:
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Date of Conference: 13-15 June 1996
- Page(s):
- 118 - 119
- Meeting Date :
- 13 Jun 1996-15 Jun 1996
- Print ISBN:
- 0-7803-3339-X
- INSPEC Accession Number:
- 5443049
- Conference Location :
- Honolulu, HI, USA
- Digital Object Identifier :
- 10.1109/VLSIC.1996.507737
- Product Type:
- Conference Publications
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