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2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell

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8 Author(s)
Hirano, H. ; Kyoto Res. Lab., Kyoto, Japan ; Honda, T. ; Moriwaki, N. ; Nakakuma, T.
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Recently, a nonvolatile memory embedded in microcontrollers has been required to have 100 ns access time at 2.0 V for mobile information terminals operating with a re-chargeable battery. To achieve this, this paper proposes new architecture for a ferroelectric nonvolatile memory (FeRAM) comprised of (a) Bitline-Driven Read Scheme and (b) Non-Relaxation Reference Cell for high speed and low voltage operation respectively. Using this architecture, a FeRAM with one transistor and one capacitor per bit (1T/1C) cell can have a performance of 100 ns access time at 2.0 V.

Published in:

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Date of Conference:

13-15 June 1996