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High-speed low-power phase-locked loops (PLLs) are an integral part of frequency synthesizers and clock recovery circuits. This paper describes the design of a 2 GHz PLL that employs a number of circuit techniques to reduce the power dissipation to 1.6 mW with a 3 V supply. Fabricated in an 18 GHz 0.6 /spl mu/m BiCMOS technology, the PLL utilizes fully-differential signals to improve the rejection of common-mode disturbances. The PLL design has a fairly standard architecture, but with the phase detector, the low-pass filter (LPF), and the voltage-controlled oscillator (VCO) merged so as to save power dissipation. The amplifier interposed between the LPF and the VCO operates at low frequencies, thus consuming negligible power.
Date of Conference: 13-15 June 1996