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3D chip stack with integrated decoupling capacitors

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8 Author(s)
Bing Dang ; IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598, USA ; Steven L. Wright ; Paul Andry ; Edmund Sprogis
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In this work, thinned Si chips were stacked using conventional C4 (controlled collapse chip connection) technology. The test chips consisted of CMOS-compatible thru-silicon via (TSV) interconnects at a pitch of 200 mum and integrated deep trench (DT) capacitors. The DC resistance of a TSV and a C4 bump is measured to be less than 10 mOmega and capacitance density of 14 muF/cm2 and 28 muF/cm2 were achieved for chip stack with o1 layer and 2 layers of interposer chips respectively. The integrated capacitors were characterized throughout the 3D chip bond and assembly process flow. Results indicated the process had negligible impact to the final capacitance value. The variation of the measured capacitance value for the final chip stacks was very small, approximately ~ 2%.

Published in:

2009 59th Electronic Components and Technology Conference

Date of Conference:

26-29 May 2009