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Pulse-width modulation pre-emphasis (PWM-PE) is a relatively new technique for compensating severe losses in wireline channels by varying the duty cycle of the transmitted pulse. The technique has been demonstrated upto 5 Gb/s and requires high-speed digital logic to accomodate narrow pulses in the transmitted bit stream. This work targets data rates beyond 10 Gb/s and extends PWM-PE to 4-PAM signals in addition to binary mode transmission. The target speed is achieved by designing the transmitter using current mode logic (CML) blocks that combine relatively large logic swings and incomplete switching of the tail current. Implemented in a 0.13-??m CMOS process to accommodate the wide output swing of 1.2 Vpp per side, the transmitter compensates upto 30 dB loss at one-half the symbol rate and operates up to 16 Gsymbols/s.