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Analysis and Design of Fully Integrated High-Power Parallel-Circuit Class-E CMOS Power Amplifiers

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9 Author(s)
Lee, O. ; Georgia Electronic Design Center (GEDC), School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA ; An, K.H. ; Kim, H. ; Lee, D.H.
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A design methodology for watt-level, fully integrated CMOS power amplifiers (PAs) is presented. It is based on the analysis of the operation and power loss mechanism of class-E PAs, which includes the effects of a finite dc-feed inductance and an impedance matching transformer. Using the proposed approach, a class-E PA with a 2 $times$ 1:2 step-up on-chip transformer was implemented in a 0.18-$mu{hbox{m}}$ CMOS technology. With a 3.3 V supply, the fully integrated PA achieves an output power of 2 W and a power-added efficiency of 31% at 1.8 GHz.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:57 ,  Issue: 3 )

Date of Publication:

March 2010

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