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Fully Depleted Polysilicon TFTs for Capacitorless 1T-DRAM

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8 Author(s)
Jin-Woo Han ; Div. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon ; Seong-Wan Ryu ; Dong-Hyun Kim ; Chung-Jin Kim
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A capacitorless 1T-DRAM is fabricated on a fully depleted poly-Si thin-film transistor (TFT) template. A heavily doped back gate with a thin back-gate dielectric is employed to facilitate the formation of a deep potential well that retains excess holes. An asymmetric double gate (n+ front gate and p+ back gate) shows a wider sensing current window than a symmetric double gate (n+ front gate and n+ back gate). This is attributed to the inherent flatband voltage between the p+ back gate and the channel inducing a deeper potential well, which allows capacitorless 1T-DRAM operation at a low back-gate voltage. The TFT capacitorless 1T-DRAM can be applied for future stackable memory for the ultrahigh density era.

Published in:

Electron Device Letters, IEEE  (Volume:30 ,  Issue: 7 )