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The design of a transceiver for packet video communication on an integrated services network

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3 Author(s)
A. Andreatos ; Dept. of Electr. Eng., Nat. Tech. Univ. of Athens, Greece ; G. De Grandi ; E. Protonotarios

The authors describe the architecture and give details on the hardware implementation of a special packet video transceiver, which is appropriate for the communication of broadcast television signals between two stations of an integrated services packet network. The system performs line processing and can detect and/or correct various kinds of errors concerning the reception of packets at the receiver, basically by replacing a wrong or missing packet or line by previously received information from the preceding scan line. Additional information is given about the design and operation of a special frequency-regulation system which the receiver uses to trigger a video digital-to-analog converter which reconverts the digitized video signal into analog form, as well as for a master clock source. This system evaluates the transmitter scanning frequency, basing the evaluation on the timing of the incoming packets. These packets are transmitted through a noisy channel (isochronous network) and are affected by random but bounded delay (jitter)

Published in:

Electrotechnical Conference, 1989. Proceedings. 'Integrating Research, Industry and Education in Energy and Communication Engineering', MELECON '89., Mediterranean

Date of Conference:

11-13 Apr 1989