Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals

A multiple-valued reconfigurable VLSI useful for improving the utilization ratio of hardware resources is proposed. Hybrid architecture based on wired programming and dynamic data-path control can be effectively employed for high utilization ratio of hardware resources with small overhead of additional hardware resources. A 2-to-1 multiplexer is provided in each cell. Accordingly, distributed control can be realized simply, so that interconnections between arithmetic logic modules and controllers become very short. Moreover, superposition of data and control signals is introduced to reduce not only complexity of interconnections but also switch block area.