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Optimization of Current-Mode MVD-ORNS Arithmetic Circuits

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5 Author(s)
Inaba, M. ; Fac. of Ind. Technol., Tsukuba Univ. of Technol., Tsukuba ; Tanno, K. ; Sawada, R. ; Tanaka, H.
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In this paper, optimization and verification of the current-mode fundamental arithmetic circuits employing MVD-ORNS are presented. MVD-ORNS is the redundant number system using logic levels in the multiple-valued logic. In order to get over weak points of ordinary circuits, the algorithms and circuit components for addition, subtraction and multiplication are reconsidered through the logical analysis and HSPICE simulation with CMOS 0.35 micrometer device parameters. As results in the 4-bit multiplier, the maximum logic level and the number of modulo operations in the series connection are successfully reduced to 29 from 49 and to 2 from 3, respectively. HSPICE simulation also shows the good results, for example the proposed switched current mirrors are very effective to bring both of the stable operation and low power dissipation to the current-mode arithmetic circuits. The proposed MVD-ORNS circuits are expected to realize the high-speed full-parallel calculation without any carry/borrow propagation.

Published in:

Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on

Date of Conference:

21-23 May 2009