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We present a delay-insensitive (DI) link that provides virtual point-to-point channels between ports at corresponding locations in two-dimensional arrays on separate chips. A communication, or event, on any particular channel is represented by its input port's address, which the link encodes, conveys, and decodes. Previous work cut pad-count by transmitting row and column addresses sequentially, appending additional column addresses for concurrent communications in the same row, which are read and written in parallel, thereby boosting throughput. However, a non-DI implementation was used off-chip (bundled-data), incurring delay and area penalties when interfaced with DI circuitry used on-chip. The link described here avoids these penalties by using a DI implementation both on- and off-chip (1-of-4 codes). We describe the transmitter's and receiver's implementation in detail, including refinements made to ensure efficient and robust operation with arrays as large as 320times960, and provide test results from two chips fabricated in a 0.18um CMOS process.
Date of Conference: 17-20 May 2009