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A modular advanced pipeline image processing accelerator

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2 Author(s)
R. A. Messner ; Dept. of Electr. & Comput. Eng., New Hampshire Univ., Durham, NH, USA ; J. Bloomfield

Next generation image processing hardware must be able to deal efficiently with the vast amounts of image data provided by advanced sensors as well as the data manipulations required by complex image processing algorithms. In this paper we outline a proposed next generation image processing accelerator being pursued by Datacube, Inc. and the University of New Hampshire. A preliminary evaluation of the proposed system is discussed providing a blueprint for specific implementation. The resulting architecture is called the Advanced image Processing Accelerator (AIPA). AIPA represents a new paradigm for the architecture of real-time image processing systems. This design eliminates the bottleneck inherent in many currently available real-time image processing solutions. Estimated Operations per Second (OPS) for this design is between 50 and 500 Giga-OPS, depending on the system configuration. The system is open architecture, is highly scalable, and cost-effective for a wide range of defense, R&D, medical, and industrial applications. The AIPA system is designed to support popular workstations and operating systems, third-party imaging accelerators and software, and commercial off-the-shelf CPUs and peripherals. A new and innovative approach to intelligent resource allocation and scheduling provides a simple method for algorithm developers to interface with the AIPA hardware. Preliminary technical design and projected performance for each subsystem is presented

Published in:

Aerospace Applications Conference, 1996. Proceedings., 1996 IEEE  (Volume:4 )

Date of Conference:

3-10 Feb 1996