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Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

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7 Author(s)
Chen, Z.X. ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore ; Yu, H.Y. ; Singh, N. ; Shen, N.S.
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This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a Si p+-i- n+ tunneling junction, the TFET with a gate length of ~ 200 nm exhibits good subthreshold swing of ~ 70 mV/dec, superior drain-induced-barrier-lowering of ~ 17 mV/V, and excellent I on - I off ratio of ~ 107 with a low I off ( ~ 7 pA/mum). The obtained 53 muA/mum I on can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.

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Electron Device Letters, IEEE  (Volume:30 ,  Issue: 7 )