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Dynamic frequency-switching clock system on a quad-core Itanium® processor

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6 Author(s)

The700mm2 65nm Itaniumreg processor codenamed Tukwila integrates four cores and a system interface with six QuickPathreg interconnect channels and four memory interconnect channels. The large die and high level of integration coupled with process variability present clock-system design challenges in the areas of power consumption and variability compensation that discuss in this paper. The clock system, which is a cascaded-PLL architecture with an initial filter PLL that receives a 133 MHz reference clock. This maiden PLL filters reference-clock jitter and outputs a 133 MHz clock to 13 downstream PLLs. Each downstream PLL has a duty-cycle corrector that monitors and corrects the end-of-route duty cycle.

Published in:

Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International

Date of Conference:

8-12 Feb. 2009