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In this paper, a shared-pixel architecture in which the Gr pixel and the Gb pixel are designed to have the same layout structure, is introduced for suppression of the Gr/Gb sensitivity imbalance. In addition, a more effective FD-boost scheme that uses both gate-to-source capacitance (CGS) and gate-to-drain capacitance (CGD) is introduced to resolve the trade-off between dark random noise and FD capability, without adding any additional pixel-drive wiring.
Published in:
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Date of Conference: 8-12 Feb. 2009
- Page(s):
- 44 - 45,45a
- Print ISBN:
- 978-1-4244-3458-9
- INSPEC Accession Number:
- 10727893
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ISSCC.2009.4977299
- Product Type:
- Conference Publications
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