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Adaptive circuits for the 0.5-V nanoscale CMOS era

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1 Author(s)
Kiyoo Itoh ; Fellow, Hitachi, Tokyo, Japan

The Vmins of logic, SRAM, and DRAM blocks were compared with a newly proposed methodology for evaluating Vmin based on speed variations, taking repair techniques into account. State-of-the-art 6T SRAM cells were then discussed in terms of Vmin and cell size. After that, many adaptive circuits and relevant technologies needed to break the 1V wall were proposed and evaluated, while taking the interconnect problem into account. Finally, 0.5 V nanoscale LSIs including mixed signal LSIs were predicted to be feasible, if relevant devices and fabrication processes are developed.

Published in:

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

Date of Conference:

8-12 Feb. 2009