Impact of line edge roughness on copper interconnects

The dimensions of transistor gates are scaling to small dimensions and the relative variation of the edge, referred to as line edge roughness (LER), is addressed as one of the critical issues for front-end technology. These local variations deteriorate the device performance [Croon etal, Tech. Dig. - Int. Electron Devices Meet. 2002, 307; Croon etal, Proceedings of the ESSDERC, 2003 (unpublished), p. 22]. However, also for backend, interconnects wires are scaling down and the relative contribution of the LER is increasing. The impact of LER for interconnects has rarely been studied yet. In this article we address the electrical performance of the resulting copper interconnects with additional LER generated with e-beam lithography. The added LER will have spatial frequencies and amplitudes that are similar to the current resists used.