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Microfabrication of ultrahigh density wafer-level thin film compliant interconnects for through-silicon-via based chip stacks

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3 Author(s)
Arunasalam, P. ; Department of Mechanical Engineering, T. J. Watson School of Engineering and Applied Science, State University of New York at Binghamton, P.O. Box 6000, New York 13902 ; Ackler, Harold D. ; Sammakia, B.G.

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1116/1.2210003 

The current trend in wafer-level three-dimensional integration is by copper-filled through-silicon vias (TSVs) which considerably minimize signal transmission time due to the short wiring length required to integrate vertically stacked chips. However, the present wire bonding technology widely used in peripheral integration of stacked chips cannot integrate TSV based chip stacks. This article describes the fabrication methodology of a thin film compliant interconnect referred to as Smart Three Axis Compliant (STAC) interconnects which can be directly integrated onto TSV based chip stacks. These batch processed compliant interconnects are successfully fabricated utilizing microelectromechanical systems technology at the wafer level by magnetron sputtering oppositely stressed layers of TiW films. Once patterned and released, STAC interconnects easily achieve input/output counts of 104/cm2 or greater, making it suitable to be directly integrated onto through-silicon-via based chip stacks.

Published in:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:24 ,  Issue: 4 )

Date of Publication:

Jul 2006

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