The causes of pitting on an active silicon surface and its impact on 0.15 and 0.30 μm n-type metal–oxide semiconductor (NMOS) and p-type metal–oxide–semiconductor (PMOS) transistors have been assessed. During polysilicon gate patterning, the gate oxide at the source/drain regions of the NMOS transistors may be etched away due to insufficient selectivity of the etch chemistry, improper etch chamber configuration, pattern density, and the adoption of dual-doped gate technology. The exposed silicon substrate has poor selectivity against the polysilicon gate, this causes Si pitting to occur on the source/drain active regions of the NMOS transistors. However, there is no significant pitting observed for the PMOS transistors due to the slower etch rate of the undoped polysilicon of the PMOS transistors. Pitting on the active areas severely degrades the device parameters, such as drive current, series resistance, and transconductance. This is worse for the 0.15 μm NMOS transistors compared to the 0.30 μm NMOS transistors. The channel resistance of the 0.30 μm transistors is much larger than any increase in the external resistance caused by the pitting. As a result, Si pitting has negligible effects on the device performance of long channel devices. © 2002 American Vacuum Society.