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Multiple layers of silicon-on-insulator for nanostructure devices

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4 Author(s)
Neudeck, Gerold W. ; School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907-1285 ; Sangwoo Pae ; Denton, J.P. ; Su, Tai-chi

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A new method for silicon-on-insulator (SOI) is presented that has very few stacking fault defects and produces multiple layers of single crystal silicon surrounded by thermal SiO2. The technique requires selective epitaxial growth, epitaxial lateral overgrowth, and chemical mechanical planarization to form SOI islands stacked in multiple layers. Islands of silicon as small as 150×150×40 nm thick were fabricated. Larger SOI islands in two SOI layers, with grown vertical interconnections between layers, were 5×500×0.1 μm. Only one stacking fault was observed in 85 000 μm2 of the first layer and none in the second layer. P-channel metal–oxide–semiconductor field effect transistors with gate lengths of less than ∼100 nm were fabricated in the thin SOI islands. They had normal current–voltage plot characteristics with less than 0.2 pA/μm of leakage current, illustrating the quality of the material in both SOI layers and at the silicon to thermal-oxide interfaces. The devices had measured subthreshold slopes of 76 mV/decade and good saturated current drives. © 1999 American Vacuum Society.

Published in:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:17 ,  Issue: 3 )