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An implementation of branch target buffer for high performance applications

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3 Author(s)
Seung Il Sonh ; Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea ; Hoon Mo Yang ; Moon Key Lee

Efficient executions of branch instructions are one of the most important issues in implementing high performance microprocessors. Branching instructions are above 20% of total instruction in most programs. BTB (Branch Target Buffer) enhances the speed of branch instruction execution by predicting the branch path, including currently executed branch instruction address, prediction information, and target address. The BTB is designed as a 4-way set associative organization with 256 branch entries. Pseudo-LRU algorithm is used for replacement of lines instead of ordinary LRU algorithm. Also IP(Instruction Pointer) chain is designed for verifying the BTB

Published in:

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Date of Conference:

6-10 Nov 1995