Referenced Items are not available for this document.
This paper describes a microprocessor that has been designed for embedded and portable application. This RISC processor offers very low power consumption and fast context switching. This architecture is based on RISC principles. The processor adopts 3-stage instruction execution pipeline and has achieved single cycle execution using a 2-phase 40 MHz clock. This results in a high instruction throughput and real-time interrupt response. This chip is implemented with 0.6 μm triple metal CMOS technology and consists of about 70 K transistors. The power dissipation is 140 mW
Published in:
Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on
Date of Conference: 6-10 Nov 1995
- Page(s):
- 488 - 491
- Meeting Date :
- 06 Nov 1995-10 Nov 1995
- Print ISBN:
- 0-7803-2624-5
- INSPEC Accession Number:
- 5262689
- Digital Object Identifier :
- 10.1109/TENCON.1995.496447
- Product Type:
- Conference Publications
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