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Hardware reduction in concurrent error detection checkers in linear analog circuits using continuous checksums

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3 Author(s)
Wong, M.W.T. ; Dept. of Electron. Eng., Hong Kong Polytech. Univ., Kowloon, Hong Kong ; Yingquan Zhou ; Yinghua Min

An algorithm proposed by Yingquan Zhou et al. (1995) for effectively reducing hardware overhead of the checking circuitry in the continuous checksums based concurrent error detection (CED) scheme in linear analog circuits is discussed. Without changing the original circuit, the algorithm generates such an appropriate coding matrix that makes the resulting checking circuitry have optimal hardware overhead

Published in:

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Date of Conference:

6-10 Nov 1995

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