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A full digital self-timed clock generation scheme

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2 Author(s)
Seunghyeon Nahm ; Dept. of Control & Instrum. Eng., Seoul Nat. Univ., South Korea ; Wonyong Sung

A full digital self-timed clock generation scheme is developed, where multiple internal clocks are self-generated for each external request. The internal clock period is designed to be the critical path delay of the internal system at all operating environments. This scheme can be applied to time-multiplexed implementations, self-timed operation, and low-power applications

Published in:

Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on

Date of Conference:

6-10 Nov 1995

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