CMOS OTA with improve performance

A new CMOS OTA which consists of a linearized source-coupled pair cascaded by a conventional CMOS OTA biased in sub-threshold region is presented. SPICE simulation results show that for /spl plusmn/5 V supply voltage, and over /spl plusmn/3 V input range, the maximum non-linear error is /spl plusmn/0.3% and the transconductance varies I/sub abc/ linearly over a wide I/sub abc/ range.