A new CMOS four-quadrant analog multiplier is presented. By means of an unique nonlinear compensation technique, the linear input range of the multiplier is extended significantly. The simulation results show that, when Vy=±3V, the nonlinear error is less than 0.94% over the ±3V input range of Vx and when Vx =±3V, the nonlinear error is less than 0.25% over the ±3V input range of Vy, with a power supply of ±5V
Published in:
Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on
Date of Conference: 6-10 Nov 1995