Referenced Items are not available for this document.
To reduce the area and developing time of the Memory Built-in Self-Test (MBIST) circuit has been challenged in the market. An architecture that could test memories different in size by only one MBIST circuit is presented in this paper. It is achieved by adding a data processing module and an address processing module into the mature and ready-made MBIST architecture. Base on this architecture, a MBIST circuit for the memories embedded in a SoC chip is successfully designed.
Published in:
Testing and Diagnosis, 2009. ICTD 2009. IEEE Circuits and Systems International Conference on
Date of Conference: 28-29 April 2009
- Page(s):
- 1 - 4
- Print ISBN:
- 978-1-4244-2587-7
- INSPEC Accession Number:
- 10665689
- Conference Location :
- Chengdu
- Digital Object Identifier :
- 10.1109/CAS-ICTD.2009.4960752
- Product Type:
- Conference Publications
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