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In many synchronous digital systems especially those used in mobile applications, the system is exposed to sever shaking that may lead to a failure in the clock generator. In this paper we present an effective method to tolerate the faults on the clock signal that are due to defects in external oscillators. Our technique utilizes no Phase-Lock Loops (PLL), no Delay-Locked Loops (DLL) and no high frequency oscillators because of their drawbacks so that it needs neither more effort to meet Electro- Magnetic Compatibility (EMC) and requirements nor extra hardware to implement DLLs. We have formally evaluated the meta-stability of our technique. This evaluation shows that our technique reliably meets the timing requirements. Furthermore, our simulation-based fault injection experiments show that our technique can tolerate all single faults on clock sources that lead to permanent stuck-at fault and masks almost 49 percents of intermittent faults.