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Limitation of the signal pin density on wiring boards

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3 Author(s)
Chiba, T. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Yamada, M. ; Kobayashi, F.

A practical limit of the signal pin density on wiring boards is investigated from the wireability point of view. The wireability problem can be expressed as a supply and demand model of two resources, i.e. wiring channels and via-holes. The limit of the signal pin density is assumed to be determined by the shortage of either of these two resources. As a measure of pin density, the average distance between adjacent signal pins, sT, is introduced. The practical limit of sT is estimated by analyzing the actual product data and experimental data. The lower bound of sT, normalized by the grid spacing, can range from 1.5 to 2.0. These results are applied as a guideline to estimate the footprint area per LSI, and to do design tradeoffs among different packaging technologies such as multichip modules (MCM)

Published in:

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on  (Volume:19 ,  Issue: 2 )