Low-voltage miller divide-by-three circuit integrated with a 1.5-GHz QVCO

In this work, the integration design of a low-voltage quadrature Miller divide-by-3 circuit are proposed and targeted for the UWB RF frequency synthesizer use. Some novel circuit schematics have been proposed and designed for the low-voltage operation. The chip was fabricated by a 0.18 mum RF-CMOS technology. The function of divide-by-3 has been successfully demonstrated together with the integration of a 1.5-GHz QVCO. Due to the parasitic capacitance loading, the measured output frequency finally has shifted to 448 MHz. The measured power consumption is about 34.8 mW drawn from the 1.2 V power supply.