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Using partial orders for trace theoretic verification of asynchronous circuits

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2 Author(s)
T. Yoneda ; Dept. of Comput. Sci., Tokyo Inst. of Technol., Japan ; T. Yoshikawa

In this paper, we propose a method to generate the reduced state spaces in which the trace theoretic verification method of asynchronous circuits works correctly and efficiently. The state space reduction is based on the stubborn set method and similar ideas, but they have been extended so that the conformance checking works correctly in the reduced state space. Our state reduction algorithm also guarantees that a kind of simple liveness properties are correctly checked. Some experimental results show the efficiency of the proposed method

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International Symposium on

Date of Conference:

18-21 Mar 1996