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Some limitations to speed-independence in asynchronous circuits

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2 Author(s)
M. E. Bush ; Centre for Concurrent Syst., South Bank Polytech., London, UK ; M. B. Josephs

Asynchronous circuits are often designed to operate correctly whatever the speeds of the elements (e.g., logic gates) out of which they are constructed. Sometimes, however, one finds that it is not possible to synthesise a speed-independent circuit that implements a given specification. The fundamental reason for these limitations to speed-independence is that certain local properties of elements manifest themselves as global properties of circuits, properties that may be incompatible with the specification to be implemented. This paper investigates several such properties (concerned with persistence, commutativity and inertia) by means of a formal analysis carried out using Josephs' Receptive Process Theory

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International Symposium on

Date of Conference:

18-21 Mar 1996