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In multichannel telecommunication networks, switching systems and processor-memory interconnects the need for conflict-free traffic assignment arises whenever packets (or requests) are to be directed from input buffers (processors) to specific outlets (modules). We present an algorithm, based on forward planning, which can be used in the above-mentioned applications for scheduling conflict-free transfers of packets from inputs to outputs. The performance of the algorithm is evaluated in the sense of throughput and delay, and compared with that of the system of distinct representatives (SDR), an earlier proposed algorithm featuring 100% assignment efficiency. Then, its worst case computational complexity is compared with that of SDR and several suboptimal low-complexity algorithms reported in literature. It is shown that forward planning of packet transmissions offers significant performance improvements if the finite capacity of buffers is taken into account. Furthermore, the proposed algorithm has the lowest order of computational complexity and permits simpler buffer organisation and access modes.