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Architectural simulation system for M.f.a.s.t

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2 Author(s)
C. H. L. Moller ; Microelectron. Div., IBM Corp., Research Triangle Park, NC, USA ; G. G. Pechanek

The paper discusses the simulation system used to verify the architecture of the Mwave folded array signal transform (M.f.a.s.t.) processor, a single chip scalable very long instruction word (VLIW) processor array being developed by IBM Microelectronics. M.f.a.s.t. simulation, at this stage of development of the architecture, is at a very high abstract level and is intended to meet the requirements of being implementation independent and permit investigation of the architecture itself, as opposed to simply verifying the congruence of the architecture and an implementation of it. The M.f.a.s.t. simulator uses a collection of functional models, implemented in C, to represent the M.f.a.s.t. architecture. The models, each reflecting the behaviour of a component of the architecture, run as independent processes and communicate among themselves using a socket mechanism. This paper discusses the merits and mechanics of this approach, and the reasons it was adopted. Two large applications and many small test cases have been written for the M.f.a.s.t. architecture and run on the M.f.a.s.t simulator. While it is difficult, for reasons that are discussed, to make easily interpretable statements about the performance of the simulator, data from these examples indicate that the simulator will emulate the execution, under average conditions, of approximately 3000 execution-unit operations per second

Published in:

Simulation Symposium, 1996., Proceedings of the 29th Annual

Date of Conference:

8-11 Apr 1996