Trench etch processes for dual damascene patterning of low-k dielectrics

The use of dual damascene patterning for integration of Cu with low-k dielectric films has introduced new challenges for plasma etch processes. With a via-first dual damascene approach, an important issue for trench etch is defect formation (i.e., oxide ridges) around vias which can degrade device reliability. The use of low-k films as the dielectric material adds additional complexity and more limitation on the etch process parameters. This article discusses the development of etch processes that meet the special requirements for Cu/low-k dual damascene trench etch. All experiments were conducted in a medium-density TEL dipole ring magnet system. The dielectric film used here was an organosilicate glass (OSG). Using C₄F₈/N₂/Ar chemistry, a trade-off was observed between etch rate and oxide ridge formation. The N₂:Ar ratio was found to be the key parameter in controlling the severity of the oxide ridges, but eliminating the ridges using the N₂:Ar ratio resulted in a low OSG etch rate and poor throughput. However, we found an alternative method which achieves a high OSG etch rate while maintaining critical dimension control and ridge-free conditions. The effect of various process parameters on the OSG etch rate and ridge formation is detailed. A comparison of experimental results against numerical simulations of C₄F₈-based bulk plasmas with varying gas flow ratios is also reported. © 2001 American Vacuum Society.