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A multilevel factorization technique for pass transistor logic

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3 Author(s)
Jaekel, A. ; VLSI Res. Group, Windsor Univ., Ont., Canada ; Jullien, G.A. ; Bandyopadhyay, S.

Pass transistor logic (PTL) networks have been used by many researchers to design fast, area efficient pipelined systems. Not much work has been done in the area of multilevel logic synthesis in PTL networks. In this paper, we have investigated the use of algebraic factorization techniques to synthesize multilevel PTL networks

Published in:

VLSI Design, 1996. Proceedings., Ninth International Conference on

Date of Conference:

3-6 Jan 1996