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IEEE Standard 1500 Compatible Delay Test Framework

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3 Author(s)
Po-Lin Chen ; Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan ; Jhih-Wei Lin ; Tsin-Yuan Chang

Rapid advances in semiconductor technology have made timing-related defects increasingly crucial in core-based system-on-chip designs. Currently, modular test strategies based on IEEE standard 1500 are applied to test the functionality of each embedded core in system-on-chip (SoC) designs but fail to verify the corresponding timing specifications. In this paper, to achieve high quality of delay tests, hardware implementation of an embedded delay test framework including the modified test wrappers and the embedded delay test mechanism is presented to build an entirely embedded delay test environment where at-speed clock is applied inside the chip to increase test accuracy. Additionally, the proposed delay test framework is capable of supporting all current solutions of core-based delay test. The experimental results successfully demonstrate the delay testing application using the proposed framework to a crypto processor with satisfying test quality and effectiveness.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:17 ,  Issue: 8 )