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A systolic array for recursive least squares estimation by inverse updates is derived by means of algorithmic engineering. The derivation of this systolic array is highly nontrivial due to the presence of data contra-flow and feedback loops in the underlying signal flow graph. This would normally prohibit pipelined processing. However, it is shown that suitable delays may be introduced into the signal flow graph by performing a simple algorithmic transformation which compensates for the interference of crossing data flows. The pipelined systolic array is then obtained by retiming the signal flow graph and applying the cut theorem
Published in:
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
(Volume:43
,
Issue:
3
)
Date of Publication: Mar 1996
- Page(s):
- 247 - 254
- ISSN :
- 1057-7130
- INSPEC Accession Number:
- 5241017
- Digital Object Identifier :
- 10.1109/82.486470
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Mar 1996
- Sponsored by :
- IEEE Circuits and Systems Society
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