By Topic

Minimization of fixed-point roundoff noise in extended state-space digital filters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
K. M. Anspach ; Sverdrup Technol. Inc., Arnold Air Force Base, TN, USA ; B. W. Bomar ; R. C. Engels ; R. D. Joseph

A technique for determining a minimum roundoff noise extended state space (e-state) realization of fixed-point recursive digital filters is developed. Previous efforts have developed such minimum roundoff noise e-state structures for the second-order e-state equation only. This new algorithm determines a minimum roundoff e-state structure for the general order e-state equation. The technique obtains a linear transformation which, when applied to the original structure, produces a minimum noise e-state structure. A combination of a conjugate gradient algorithm and a variable metric algorithm is employed to determine the transformation coefficients. The e-state roundoff noise characteristics are illustrated by numerical examples. It is found that the minimum-noise e-state structure can have lower roundoff noise than the conventional minimum-noise structure, since fewer state variables are actually computed. In an e-state structure an Nth-order filter where N=LM can be implemented by M difference equations of order L resulting in a computational complexity of O[L(M+1)2]. One advantage of e-state structures, compared to other realizations, is the use of fewer but longer inner products which pipelined digital signal processors are designed to handle efficiently

Published in:

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:43 ,  Issue: 3 )