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A novel CMOS frequency doubler circuit is presented in this paper. A common source transistor pair biased at threshold is used to rectify the input signal in both the positive and negative cycles. The rectified signals are then subtracted to generate a double frequency signal. Measurement results show that there is more than 20 dB fundamental rejection with the input power level ranging from -20 dBm to -10.3 dBm. The 3rd and 4th harmonic rejections are above 20 dB with input power up to -10 dBm without any on-chip or off-chip filtering.
Sarnoff Symposium, 2009. SARNOFF '09. IEEE
Date of Conference: March 30 2009-April 1 2009