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We consider performance modeling of yield learning in semiconductor manufacturing. Attention is restricted to the learning of defect reduction in the wafer fabrication stage of IC production. The performance measures of primary interest are the rate of yield improvement and the return on investment for defect reduction strategies. Based on the inputs from fabs, we describe the defect reduction process and learning cycle, and model it to optimize the economic benefits of fast yield improvement. Potential approaches to analyze the model are proposed. We discuss the impact of resources deployed for yield learning on fab performance.