By Topic

Capital productivity-challenge and opportunity

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Rowe, W. ; IBM Corp., Essex Junction, VT, USA

Summary form only given. Controlling the rapidly increasing costs of semiconductor wafer fabricators presents a serious challenge to the semiconductor industry. SEMATECH, in cooperation with its members and SEMI/SEMATECH suppliers has developed a methodology to maintain the historic price per function decline rate for semiconductor products. A series of 0.25 micron generation fab cost models were developed at SEMATECH. The models incorporated advanced logic and DRAM processes, operational and financial inputs and equipment cost and performance goals. Wafer processing costs from the model were compared to affordable costs developed by the SEMATECH Competitive Analysis Group. The result of this process has been a set of mutually agreed upon cost and performance targets for the 0.25 micron generation of equipment. Equipment meeting those targets will be more cost effective than that currently available. High operating efficiency as measured by overall equipment effectiveness (OEE) is essential to achieving improved capital productivity goals.

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1995. ASMC 95 Proceedings. IEEE/SEMI 1995

Date of Conference:

13-15 Nov 1995